# 1 "FWlib/apt32f102_adc.c"
# 1 "E:\\APT_Landscape_mode\\APT32F1023_New\\Source//"
# 1 "<built-in>"
# 1 "<command-line>"
# 1 "FWlib/apt32f102_adc.c"
# 19 "FWlib/apt32f102_adc.c"
# 1 "include/apt32f102_adc.h" 1
# 23 "include/apt32f102_adc.h"
# 1 "include/apt32f102.h" 1
# 23 "include/apt32f102.h"
# 1 "include/apt32f102_types_local.h" 1
# 63 "include/apt32f102_types_local.h"
typedef signed char S8_T;
typedef short S16_T;
typedef long S32_T;


typedef unsigned char U8_T;
typedef unsigned short U16_T;
typedef unsigned long U32_T;
typedef unsigned long long U64_T;


typedef float F32_T;
typedef double F64_T;


typedef U8_T B_T;
# 100 "include/apt32f102_types_local.h"
typedef enum {ENABLE = 1, DISABLE = !ENABLE} ClockStatus, FunctionalStatus;
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;




typedef volatile U32_T CSP_REGISTER_T;
typedef volatile U16_T CSP_REGISTER16_T;
typedef volatile U8_T CSP_REGISTER8_T;




typedef unsigned char UINT8;
typedef signed char SINT8;


typedef unsigned short UINT16;
typedef signed short SINT16;


typedef unsigned long UINT32;
typedef signed long SINT32;

typedef void VOID;
typedef signed char CHAR;
typedef unsigned char BOOL;
typedef signed long TIME_T;

typedef float SINGLE;



typedef double DOUBLE;

typedef struct
{
  unsigned bit0 : 1;
  unsigned bit1 : 1;
  unsigned bit2 : 1;
  unsigned bit3 : 1;
  unsigned bit4 : 1;
  unsigned bit5 : 1;
  unsigned bit6 : 1;
  unsigned bit7 : 1;
} REG8;

typedef struct
{
  unsigned bit0 : 1;
  unsigned bit1 : 1;
  unsigned bit2 : 1;
  unsigned bit3 : 1;
  unsigned bit4 : 1;
  unsigned bit5 : 1;
  unsigned bit6 : 1;
  unsigned bit7 : 1;
  unsigned bit8 : 1;
  unsigned bit9 : 1;
  unsigned bit10: 1;
  unsigned bit11: 1;
  unsigned bit12: 1;
  unsigned bit13: 1;
  unsigned bit14: 1;
  unsigned bit15: 1;
} REG16;






typedef char STRING_3[4];
typedef char STRING_5[6];
typedef char STRING_8[9];
typedef char STRING_10[11];
typedef char STRING_12[13];
typedef char STRING_16[17];
typedef char STRING_24[25];
typedef char STRING_30[31];
typedef char STRING_32[33];
typedef char STRING_48[49];
typedef char STRING_50[51];
typedef char STRING_60[61];
typedef char STRING_80[81];
typedef char STRING_132[133];
typedef char STRING_256[257];
typedef char STRING_512[513];
# 24 "include/apt32f102.h" 2
# 1 "include/apt32f102_ck801.h" 1
# 85 "include/apt32f102_ck801.h"
typedef enum IRQn
{

        ISR_Restart = -32,
        ISR_Misaligned_Access = -31,
        ISR_Access_Error = -30,
        ISR_Divided_By_Zero = -29,
        ISR_Illegal = -28,
        ISR_Privlege_Violation = -27,
        ISR_Trace_Exection = -26,
        ISR_Breakpoint_Exception = -25,
        ISR_Unrecoverable_Error = -24,
        ISR_Idly4_Error = -23,
        ISR_Auto_INT = -22,
        ISR_Auto_FINT = -21,
        ISR_Reserved_HAI = -20,
        ISR_Reserved_FP = -19,
        ISR_TLB_Ins_Empty = -18,
        ISR_TLB_Data_Empty = -17,

        INTC_CORETIM_IRQn = 0,
        INTC_TIME1_IRQn = 1,
        INTC_UART0_IRQn = 2,
        INTC_GPIOA2_IRQn = 8,
} IRQn_Type;


void INTC_Init(void);
void force_interrupt(IRQn_Type IRQn);

void CK_CPU_EnAllNormalIrq(void);
void CK_CPU_DisAllNormalIrq(void);
# 25 "include/apt32f102.h" 2




typedef struct {
 volatile unsigned int ReservedA[4];
 volatile unsigned int CORET_CSR;
 volatile unsigned int CORET_RVR;
 volatile unsigned int CORET_CVR;
 volatile unsigned int CORET_CALIB;
 volatile unsigned int ReservedB[56];
 volatile unsigned int ISER;
 volatile unsigned int ReservedC[15];
 volatile unsigned int IWER;
 volatile unsigned int ReservedD[15];
 volatile unsigned int ICER;
 volatile unsigned int ReservedE[15];
 volatile unsigned int IWDR;
 volatile unsigned int ReservedF[15];
 volatile unsigned int ISPR;
 volatile unsigned int ReservedG[31];
 volatile unsigned int ICPR;
 volatile unsigned int ReservedH[31];
 volatile unsigned int IABR;
 volatile unsigned int ReservedI[63];
 volatile unsigned int IPR[8];
 volatile unsigned int ReservedJ[504];
 volatile unsigned int ISR;
 volatile unsigned int IPTR;
} CSP_CK801_T;



typedef volatile struct {
 volatile unsigned int IDR ;
 volatile unsigned int CEDR ;
 volatile unsigned int SRR ;
 volatile unsigned int CMR ;
 volatile unsigned int CR ;
 volatile unsigned int MR ;
 volatile unsigned int FM_ADDR ;
 volatile unsigned int Reserved ;
 volatile unsigned int KR ;
 volatile unsigned int IMCR ;
 volatile unsigned int RISR ;
 volatile unsigned int MISR ;
 volatile unsigned int ICR ;
} CSP_IFC_T ;



typedef volatile struct {
 volatile unsigned int IDCCR;
 volatile unsigned int GCER;
 volatile unsigned int GCDR;
 volatile unsigned int GCSR;
 volatile unsigned int CKST;
 volatile unsigned int RAMCHK;
 volatile unsigned int EFLCHK;
 volatile unsigned int SCLKCR;
 volatile unsigned int PCLKCR;
 volatile unsigned int _RSVD0;
 volatile unsigned int PCER0;
 volatile unsigned int PCDR0;
 volatile unsigned int PCSR0;
 volatile unsigned int PCER1;
 volatile unsigned int PCDR1;
 volatile unsigned int PCSR1;
 volatile unsigned int OSTR;
 volatile unsigned int _RSVD1;
 volatile unsigned int _RSVD2;
 volatile unsigned int LVDCR;
 volatile unsigned int CLCR;
 volatile unsigned int PWRCR;
 volatile unsigned int PWRKEY;
 volatile unsigned int _RSVD3;
 volatile unsigned int _RSVD4;
 volatile unsigned int OPT1;
 volatile unsigned int OPT0;
 volatile unsigned int WKCR;
 volatile unsigned int _RSVD5;
 volatile unsigned int IMER;
 volatile unsigned int IMDR;
 volatile unsigned int IMCR;
 volatile unsigned int IAR;
 volatile unsigned int ICR;
 volatile unsigned int RISR;
 volatile unsigned int MISR;
 volatile unsigned int RSR;
 volatile unsigned int EXIRT;
 volatile unsigned int EXIFT;
 volatile unsigned int EXIER;
 volatile unsigned int EXIDR;
 volatile unsigned int EXIMR;
 volatile unsigned int EXIAR;
 volatile unsigned int EXICR;
 volatile unsigned int EXIRS;
 volatile unsigned int IWDCR;
 volatile unsigned int IWDCNT;
 volatile unsigned int IWDEDR;
 volatile unsigned int IOMAP0;
 volatile unsigned int IOMAP1;
 volatile unsigned int CINF0;
 volatile unsigned int CINF1;
 volatile unsigned int FINF0;
 volatile unsigned int FINF1;
 volatile unsigned int FINF2;
 volatile unsigned int _RSVD6;
 volatile unsigned int ERRINF;
 volatile unsigned int UID0 ;
 volatile unsigned int UID1 ;
 volatile unsigned int UID2 ;
 volatile unsigned int PWROPT;
 volatile unsigned int EVTRG;
 volatile unsigned int EVPS;
 volatile unsigned int EVSWF;
 volatile unsigned int UREG0;
 volatile unsigned int UREG1;
 volatile unsigned int UREG2;
 volatile unsigned int UREG3;
} CSP_SYSCON_T;



 typedef volatile struct
 {
    volatile unsigned int EN;
    volatile unsigned int SWTRG;
    volatile unsigned int CH0CON0;
    volatile unsigned int CH0CON1;
    volatile unsigned int CH1CON0;
    volatile unsigned int CH1CON1;
    volatile unsigned int CH2CON0;
    volatile unsigned int CH2CON1;
 volatile unsigned int _RSVD0;
 volatile unsigned int _RSVD1;
 volatile unsigned int _RSVD2;
 volatile unsigned int _RSVD3;
    volatile unsigned int CH3CON;
 volatile unsigned int CH4CON;
 volatile unsigned int CH5CON;
 volatile unsigned int CH6CON;
 volatile unsigned int CH7CON;
 } CSP_ETCB_T, *CSP_ETCB_PTR;



typedef volatile struct
{
   volatile unsigned int TCH_CCR;
   volatile unsigned int TCH_CON0;
   volatile unsigned int TCH_CON1;
   volatile unsigned int TCH_SCCR;
   volatile unsigned int TCH_SENPRD;
   volatile unsigned int TCH_VALBUF;
   volatile unsigned int TCH_SENCNT;
   volatile unsigned int TCH_TCHCNT;
   volatile unsigned int TCH_THR;
   volatile unsigned int Reserved0;
   volatile unsigned int TCH_RISR;
   volatile unsigned int TCH_IER;
   volatile unsigned int TCH_ICR;
   volatile unsigned int TCH_RWSR;
   volatile unsigned int TCH_OVW_THR;
   volatile unsigned int TCH_OVF;
   volatile unsigned int TCH_OVT;
   volatile unsigned int TCH_SYNCR;
   volatile unsigned int TCH_EVTRG;
   volatile unsigned int TCH_EVPS;
   volatile unsigned int TCH_EVSWF;
} CSP_TKEY_T, *CSP_TKEY_PTR;



typedef volatile struct
{
   volatile unsigned int TCH_CHVAL[18];
   volatile unsigned int TCH_SEQCON[18];
} CSP_TKEYBUF_T, *CSP_TKEYBUF_PTR;



 typedef volatile struct
 {
    volatile unsigned int ECR;
    volatile unsigned int DCR;
    volatile unsigned int PMSR;
    volatile unsigned int Reserved0;
    volatile unsigned int CR;
    volatile unsigned int MR;
    volatile unsigned int SHR;
    volatile unsigned int CSR;
    volatile unsigned int SR;
    volatile unsigned int IER;
    volatile unsigned int IDR;
    volatile unsigned int IMR;
    volatile unsigned int SEQ[16];
    volatile unsigned int PRI;
    volatile unsigned int TDL0;
    volatile unsigned int TDL1;
    volatile unsigned int SYNCR;
    volatile unsigned int Reserved1;
    volatile unsigned int Reserved2;
    volatile unsigned int EVTRG;
    volatile unsigned int EVPS;
    volatile unsigned int EVSWF;
    volatile unsigned int ReservedD[27];
    volatile unsigned int DR[16];
    volatile unsigned int CMP0;
    volatile unsigned int CMP1;
 volatile unsigned int DRMASK;
 } CSP_ADC12_T, *CSP_ADC12_PTR;



 typedef volatile struct
 {
    volatile unsigned int CONLR;
    volatile unsigned int CONHR;
    volatile unsigned int WODR;
    volatile unsigned int SODR;
    volatile unsigned int CODR;
    volatile unsigned int ODSR;
    volatile unsigned int PSDR;
    volatile unsigned int FLTEN;
    volatile unsigned int PUDR;
    volatile unsigned int DSCR;
    volatile unsigned int OMCR;
    volatile unsigned int IECR;
 volatile unsigned int IEER;
 volatile unsigned int IEDR;
 } CSP_GPIO_T, *CSP_GPIO_PTR;

 typedef volatile struct
 {
 volatile unsigned int IGRPL;
    volatile unsigned int IGRPH;
 volatile unsigned int IGREX;
    volatile unsigned int IO_CLKEN;
 } CSP_IGRP_T, *CSP_IGRP_PTR;



 typedef volatile struct
 {
    volatile unsigned int DATA;
    volatile unsigned int SR;
    volatile unsigned int CTRL;
    volatile unsigned int ISR;
    volatile unsigned int BRDIV;
    volatile unsigned int ReservedA[20];
 } CSP_UART_T, *CSP_UART_PTR;



typedef struct
{
 volatile unsigned int CR0;
 volatile unsigned int CR1;
 volatile unsigned int DR;
 volatile unsigned int SR;
 volatile unsigned int CPSR;
 volatile unsigned int IMSCR;
 volatile unsigned int RISR;
 volatile unsigned int MISR;
 volatile unsigned int ICR;
} CSP_SSP_T, *CSP_SSP_PTR;



typedef struct
{
 volatile unsigned int CR;
 volatile unsigned int TXCR0;
 volatile unsigned int TXCR1;
 volatile unsigned int TXBUF;
 volatile unsigned int RXCR0;
 volatile unsigned int RXCR1;
 volatile unsigned int RXCR2;
 volatile unsigned int RXBUF;
 volatile unsigned int RISR;
 volatile unsigned int MISR;
 volatile unsigned int IMCR;
 volatile unsigned int ICR;
} CSP_SIO_T, *CSP_SIO_PTR;



 typedef volatile struct
 {
    unsigned int CR;
    unsigned int TADDR;
    unsigned int SADDR;
    unsigned int ReservedD;
    unsigned int DATA_CMD;
    unsigned int SS_SCLH;
    unsigned int SS_SCLL;
    unsigned int FS_SCLH;
    unsigned int FS_SCLL;
    unsigned int ReservedA;
    unsigned int ReservedC;
    unsigned int RX_FLSEL;
    unsigned int TX_FLSEL;
    unsigned int RX_FL;
    unsigned int TX_FL;
    unsigned int ENABLE;
    unsigned int STATUS;
    unsigned int ReservedB;
    unsigned int SDA_TSETUP;
    unsigned int SDA_THOLD;
    unsigned int SPKLEN;

    unsigned int ReservedE;
 unsigned int MISR;
    unsigned int IMSCR;
    unsigned int RISR;
    unsigned int ICR;
    unsigned int ReservedF;
    unsigned int SCL_TOUT;
    unsigned int SDA_TOUT;
    unsigned int TX_ABRT;
    unsigned int GCALL;
    unsigned int NACK;
 } CSP_I2C_T, *CSP_I2C_PTR;



 typedef struct
 {
    volatile unsigned int CADATAH;
    volatile unsigned int CADATAL;
    volatile unsigned int CACON;
    volatile unsigned int INTMASK;
 } CSP_CA_T, *CSP_CA_PTR;



 typedef struct
 {
 volatile unsigned int CEDR;
 volatile unsigned int RSSR;
 volatile unsigned int PSCR;
 volatile unsigned int CR;
 volatile unsigned int SYNCR;
 volatile unsigned int GLDCR;
 volatile unsigned int GLDCFG;
 volatile unsigned int GLDCR2;
 volatile unsigned int Reserved0;
 volatile unsigned int PRDR;
 volatile unsigned int Reserved1;
 volatile unsigned int CMPA;
 volatile unsigned int CMPB;
 volatile unsigned int Reserved2;
 volatile unsigned int Reserved3;
 volatile unsigned int CMPLDR;
 volatile unsigned int CNT;
 volatile unsigned int AQLDR;
 volatile unsigned int AQCRA;
 volatile unsigned int AQCRB;
 volatile unsigned int Reserved4;
 volatile unsigned int Reserved5;
 volatile unsigned int Reserved6;
 volatile unsigned int AQOSF;
 volatile unsigned int AQCSF;
 volatile unsigned int Reserved7;
 volatile unsigned int Reserved8;
 volatile unsigned int Reserved9;
 volatile unsigned int Reserved10;
 volatile unsigned int Reserved11;
 volatile unsigned int Reserved12;
 volatile unsigned int Reserved13;
 volatile unsigned int Reserved14;
 volatile unsigned int Reserved15;
 volatile unsigned int Reserved16;
 volatile unsigned int Reserved17;
 volatile unsigned int Reserved18;
 volatile unsigned int Reserved19;
 volatile unsigned int Reserved20;
 volatile unsigned int Reserved21;
 volatile unsigned int Reserved22;
 volatile unsigned int Reserved23;
 volatile unsigned int Reserved24;
 volatile unsigned int Reserved25;
 volatile unsigned int Reserved26;
 volatile unsigned int Reserved27;
 volatile unsigned int TRGFTCR;
 volatile unsigned int TRGFTWR;
 volatile unsigned int EVTRG;
 volatile unsigned int EVPS;
 volatile unsigned int EVCNTINIT;
 volatile unsigned int EVSWF;
 volatile unsigned int RISR;
 volatile unsigned int MISR;
 volatile unsigned int IMCR;
 volatile unsigned int ICR;
 volatile unsigned int REGLINK;

 }CSP_GPT_T,*CSP_GPT_PTR;



 typedef struct
 {
   volatile unsigned int CEDR;
   volatile unsigned int RSSR;
   volatile unsigned int PSCR;
   volatile unsigned int CR;
   volatile unsigned int SYNCR;
   volatile unsigned int GLDCR;
   volatile unsigned int GLDCFG;
   volatile unsigned int GLDCR2;
   volatile unsigned int HRCFG;
   volatile unsigned int PRDR;
   volatile unsigned int PHSR;
   volatile unsigned int CMPA;
   volatile unsigned int CMPB;
   volatile unsigned int CMPC;
   volatile unsigned int CMPD;
   volatile unsigned int CMPLDR;
   volatile unsigned int CNT;
   volatile unsigned int AQLDR;
   volatile unsigned int AQCRA;
   volatile unsigned int AQCRB;
   volatile unsigned int AQCRC;
   volatile unsigned int AQCRD;
   volatile unsigned int AQTSCR;
   volatile unsigned int AQOSF;
   volatile unsigned int AQCSF;
   volatile unsigned int DBLDR;
   volatile unsigned int DBCR;
   volatile unsigned int DPSCR;
   volatile unsigned int DBDTR;
   volatile unsigned int DBDTF;
   volatile unsigned int CPCR;
   volatile unsigned int EMSRC;
   volatile unsigned int EMSRC2;
   volatile unsigned int EMPOL;
   volatile unsigned int EMECR;
   volatile unsigned int EMOSR;
   volatile unsigned int Reserved;
   volatile unsigned int EMSLSR;
   volatile unsigned int EMSLCLR;
   volatile unsigned int EMHLSR;
   volatile unsigned int EMHLCLR;
   volatile unsigned int EMFRCR;
   volatile unsigned int EMRISR;
   volatile unsigned int EMMISR;
   volatile unsigned int EMIMCR;
   volatile unsigned int EMICR;
   volatile unsigned int TRGFTCR;
   volatile unsigned int TRGFTWR;
   volatile unsigned int EVTRG;
   volatile unsigned int EVPS;
   volatile unsigned int EVCNTINIT;
   volatile unsigned int EVSWF;
   volatile unsigned int RISR;
   volatile unsigned int MISR;
   volatile unsigned int IMCR;
   volatile unsigned int ICR;
   volatile unsigned int REGLINK;
   volatile unsigned int REGLINK2;
   volatile unsigned int REGPROT;
} CSP_EPT_T, *CSP_EPT_PTR;



 typedef volatile struct
 {
   volatile unsigned int CEDR;
   volatile unsigned int RSSR;
   volatile unsigned int PSCR;
   volatile unsigned int CR;
   volatile unsigned int SYNCR;
   volatile unsigned int PRDR;
   volatile unsigned int CMP;
   volatile unsigned int CNT;
   volatile unsigned int TRGFTCR;
   volatile unsigned int TRGFTWR;
   volatile unsigned int EVTRG;
   volatile unsigned int EVPS;
   volatile unsigned int EVSWF;
   volatile unsigned int RISR;
   volatile unsigned int MISR;
   volatile unsigned int IMCR;
   volatile unsigned int ICR;
} CSP_LPT_T, *CSP_LPT_PTR;



 typedef struct
 {
   volatile unsigned int RSSR;
   volatile unsigned int CR;
   volatile unsigned int PSCR;
   volatile unsigned int PRDR;
   volatile unsigned int CMP;
   volatile unsigned int CNT;
   volatile unsigned int EVTRG;
   volatile unsigned int EVPS;
   volatile unsigned int EVCNTINTI;
   volatile unsigned int EVSWF;
   volatile unsigned int RISR;
   volatile unsigned int IMCR;
   volatile unsigned int MISR;
   volatile unsigned int ICR;
} CSP_BT_T, *CSP_BT_PTR;



typedef struct
{
   volatile unsigned int IDR;
   volatile unsigned int CEDR;
   volatile unsigned int SRR;
   volatile unsigned int CR;
   volatile unsigned int SEED;
   volatile unsigned int DATAIN;
   volatile unsigned int DATAOUT;

} CSP_CRC_T, *CSP_CRC_PTR;



 typedef struct
 {
   volatile unsigned int TIMR;
   volatile unsigned int DATR;
   volatile unsigned int CR;
   volatile unsigned int CCR;
   volatile unsigned int ALRAR;
   volatile unsigned int ALRBR;
   volatile unsigned int SSR;
   volatile unsigned int CAL;
   volatile unsigned int RISR;
   volatile unsigned int IMCR;
   volatile unsigned int MISR;
   volatile unsigned int ICR;
   volatile unsigned int KEY;
   volatile unsigned int EVTRG;
   volatile unsigned int EVPS;
   volatile unsigned int EVSWF;
} CSP_RTC_T, *CSP_RTC_PTR;




 typedef struct
 {
  volatile unsigned int CR;
  volatile unsigned int CFGR;
  volatile unsigned int RISR;
  volatile unsigned int MISR;
  volatile unsigned int IMCR;
  volatile unsigned int ICR;
 }CSP_WWDT_T,*CSP_WWDT_PTR;



 typedef struct
 {
  volatile S32_T DIVIDENT;
  volatile S32_T DIVISOR;
  volatile S32_T QUOTIENT;
  volatile S32_T REMAIN;
  volatile unsigned int CR;
 }CSP_HWD_T,*CSP_HWD_PTR;
# 691 "include/apt32f102.h"
extern CSP_CK801_T *CK801 ;

extern CSP_IFC_T *IFC ;
extern CSP_SYSCON_T *SYSCON ;
extern CSP_ETCB_T *ETCB ;

extern CSP_TKEY_T *TKEY ;
extern CSP_TKEYBUF_T *TKEYBUF ;
extern CSP_ADC12_T *ADC0 ;

extern CSP_GPIO_T *GPIOA0 ;
extern CSP_GPIO_T *GPIOB0 ;
extern CSP_IGRP_T *GPIOGRP ;

extern CSP_UART_T *UART0 ;
extern CSP_UART_T *UART1 ;
extern CSP_UART_T *UART2 ;
extern CSP_SSP_T *SPI0 ;
extern CSP_SIO_T *SIO0 ;
extern CSP_I2C_T *I2C0 ;
extern CSP_CA_T *CA0 ;

extern CSP_GPT_T *GPT0 ;

extern CSP_EPT_T *EPT0 ;

extern CSP_LPT_T *LPT ;
extern CSP_HWD_T *HWD ;
extern CSP_WWDT_T *WWDT ;
extern CSP_BT_T *BT0 ;
extern CSP_BT_T *BT1 ;

extern CSP_CRC_T *CRC ;
extern CSP_RTC_T *RTC ;


void MisalignedHandler(void) __attribute__((isr));
void IllegalInstrHandler(void) __attribute__((isr));
void AccessErrHandler(void) __attribute__((isr));
void BreakPointHandler(void) __attribute__((isr));
void UnrecExecpHandler(void) __attribute__((isr));
void Trap0Handler(void) __attribute__((isr));
void Trap1Handler(void) __attribute__((isr));
void Trap2Handler(void) __attribute__((isr));
void Trap3Handler(void) __attribute__((isr));
void PendTrapHandler(void) __attribute__((isr));

void CORETHandler(void) __attribute__((isr));
void SYSCONIntHandler(void) __attribute__((isr));
void IFCIntHandler(void) __attribute__((isr));
void ADCIntHandler(void) __attribute__((isr));
void EPT0IntHandler(void) __attribute__((isr));
void WWDTHandler(void) __attribute__((isr));
void EXI0IntHandler(void) __attribute__((isr));
void EXI1IntHandler(void) __attribute__((isr));
void EXI2to3IntHandler(void) __attribute__((isr));
void EXI4to9IntHandler(void) __attribute__((isr));
void EXI10to15IntHandler(void) __attribute__((isr));
void UART0IntHandler(void) __attribute__((isr));
void UART1IntHandler(void) __attribute__((isr));
void UART2IntHandler(void) __attribute__((isr));
void I2CIntHandler(void) __attribute__((isr));
void GPT0IntHandler(void) __attribute__((isr));
void LEDIntHandler(void) __attribute__((isr));
void TKEYIntHandler(void) __attribute__((isr));
void SPI0IntHandler(void) __attribute__((isr));
void SIO0IntHandler(void) __attribute__((isr));
void CNTAIntHandler(void) __attribute__((isr));
void RTCIntHandler(void) __attribute__((isr));
void LPTIntHandler(void) __attribute__((isr));
void BT0IntHandler(void) __attribute__((isr));
void BT1IntHandler(void) __attribute__((isr));

extern int __divsi3 (int a, int b);
extern unsigned int __udivsi3 (unsigned int a, unsigned int b);
extern int __modsi3 (int a, int b);
extern unsigned int __umodsi3 (unsigned int a, unsigned int b);
extern void delay_nms(unsigned int t);
extern void delay_nus(unsigned int t);
# 24 "include/apt32f102_adc.h" 2
# 46 "include/apt32f102_adc.h"
typedef enum
{
 ADC12_SWRST = ((CSP_REGISTER_T)(0x01ul << 0)),
 ADC12_ADCEN = ((CSP_REGISTER_T)(0x01ul << 1)),
 ADC12_ADCDIS = ((CSP_REGISTER_T)(0x01ul << 2)),
 ADC12_START = ((CSP_REGISTER_T)(0x01ul << 3)),
 ADC12_STOP = ((CSP_REGISTER_T)(0x01ul << 4)),
 ADC12_SWTRG = ((CSP_REGISTER_T)(0x01ul << 5)),
 ADC12_AVGEN = ((CSP_REGISTER_T)(0x01ul << 12)),
 ADC12_AVGDIS = ((CSP_REGISTER_T)(0x00ul << 12)),
}ADC12_Control_TypeDef;



typedef enum
{

 ADC12_EOC = ((CSP_REGISTER_T)(0x01ul << 0)),
 ADC12_READY = ((CSP_REGISTER_T)(0x01ul << 1)),
 ADC12_OVR = ((CSP_REGISTER_T)(0x01ul << 2)),
 ADC12_CMP0H = ((CSP_REGISTER_T)(0x01ul << 4)),
 ADC12_CMP0L = ((CSP_REGISTER_T)(0x01ul << 5)),
 ADC12_CMP1H = ((CSP_REGISTER_T)(0x01ul << 6)),
 ADC12_CMP1L = ((CSP_REGISTER_T)(0x01ul << 7)),
 ADC12_SEQ_END0 = ((CSP_REGISTER_T)(0x01ul << 16)),
 ADC12_SEQ_END1 = ((CSP_REGISTER_T)(0x01ul << 17)),
 ADC12_SEQ_END2 = ((CSP_REGISTER_T)(0x01ul << 18)),
 ADC12_SEQ_END3 = ((CSP_REGISTER_T)(0x01ul << 19)),
 ADC12_SEQ_END4 = ((CSP_REGISTER_T)(0x01ul << 20)),
 ADC12_SEQ_END5 = ((CSP_REGISTER_T)(0x01ul << 21)),
 ADC12_SEQ_END6 = ((CSP_REGISTER_T)(0x01ul << 22)),
 ADC12_SEQ_END7 = ((CSP_REGISTER_T)(0x01ul << 23)),
 ADC12_SEQ_END8 = ((CSP_REGISTER_T)(0x01ul << 24)),
 ADC12_SEQ_END9 = ((CSP_REGISTER_T)(0x01ul << 25)),
 ADC12_SEQ_END10 = ((CSP_REGISTER_T)(0x01ul << 26)),
 ADC12_SEQ_END11 = ((CSP_REGISTER_T)(0x01ul << 27)),
 ADC12_SEQ_END12 = ((CSP_REGISTER_T)(0x01ul << 28)),
 ADC12_SEQ_END13 = ((CSP_REGISTER_T)(0x01ul << 29)),
 ADC12_SEQ_END14 = ((CSP_REGISTER_T)(0x01ul << 30)),
 ADC12_SEQ_END15 = ((CSP_REGISTER_T)(0x01ul << 31)),

 ADC12_ADCENS = ((CSP_REGISTER_T)(0x01ul << 8)),
 ADC12_CTCVS = ((CSP_REGISTER_T)(0x01ul << 9))
}
ADC12_IMR_TypeDef;



typedef enum
{
 ADC_CLK_CR = ((CSP_REGISTER_T)(0x01ul << 1)),
 ADC12_IPIDCODE_MASK = ((CSP_REGISTER_T)(0x3FFFFFFul << 4)),
 ADC_DEBUG_MODE = ((CSP_REGISTER_T)(0x01ul << 31))
}
ADC12_CLK_TypeDef;



typedef enum
{
 ADC12_12BIT = 1,
 ADC12_10BIT = 0,
 ADC12_10BITor12BIT = ((CSP_REGISTER_T)(0x01ul<<31))
}ADC12_10bitor12bit_TypeDef;



typedef enum
{
 One_shot_mode = 0,
 Continuous_mode = 1,
 CONTCV = (CSP_REGISTER_T)0x01<<31
}ADC12_ConverMode_TypeDef;



typedef enum
{
 NBRCMP0_TypeDef = 0,
 NBRCMP1_TypeDef = 1
}
ADC12_NBRCMPx_TypeDef;



typedef enum
{
 NBRCMPX_L_TypeDef = 0,
 NBRCMPX_H_TypeDef = 1
}
ADC12_NBRCMPx_HorL_TypeDef;



typedef enum
{
  ADC12_ADCIN0 = (CSP_REGISTER_T)(0x0ul),
  ADC12_ADCIN1 = (CSP_REGISTER_T)(0x1ul),
  ADC12_ADCIN2 = (CSP_REGISTER_T)(0x2ul),
  ADC12_ADCIN3 = (CSP_REGISTER_T)(0x3ul),
  ADC12_ADCIN4 = (CSP_REGISTER_T)(0x4ul),
  ADC12_ADCIN5 = (CSP_REGISTER_T)(0x5ul),
  ADC12_ADCIN6 = (CSP_REGISTER_T)(0x6ul),
  ADC12_ADCIN7 = (CSP_REGISTER_T)(0x7ul),
  ADC12_ADCIN8 = (CSP_REGISTER_T)(0x8ul),
  ADC12_ADCIN9 = (CSP_REGISTER_T)(0x9ul),
  ADC12_ADCIN10 = (CSP_REGISTER_T)(0x0Aul),
  ADC12_ADCIN11 = (CSP_REGISTER_T)(0x0Bul),
  ADC12_ADCIN12 = (CSP_REGISTER_T)(0x0Cul),
  ADC12_ADCIN13 = (CSP_REGISTER_T)(0x0Dul),
  ADC12_ADCIN14 = (CSP_REGISTER_T)(0x0Eul),
  ADC12_ADCIN15 = (CSP_REGISTER_T)(0x0Ful),
# 170 "include/apt32f102_adc.h"
  ADC12_INTVREF = (CSP_REGISTER_T)(0x1Cul),
  ADC12_DIV4_VDD = (CSP_REGISTER_T)(0x1Dul),
  ADC12_VSS = (CSP_REGISTER_T)(0x1Eul),
}
ADC12_InputSet_TypeDef;




typedef enum
{
  ADC12_CV_RepeatNum1 = (CSP_REGISTER_T)(0x0ul<<8)|(0x0ul<<13),
  ADC12_CV_RepeatNum2 = (CSP_REGISTER_T)(0x1ul<<8)|(0x1ul<<13),
  ADC12_CV_RepeatNum4 = (CSP_REGISTER_T)(0x2ul<<8)|(0x2ul<<13),
  ADC12_CV_RepeatNum8 = (CSP_REGISTER_T)(0x3ul<<8)|(0x3ul<<13),
  ADC12_CV_RepeatNum16 = (CSP_REGISTER_T)(0x4ul<<8)|(0x4ul<<13),
  ADC12_CV_RepeatNum32 = (CSP_REGISTER_T)(0x5ul<<8)|(0x5ul<<13),
  ADC12_CV_RepeatNum64 = (CSP_REGISTER_T)(0x6ul<<8)|(0x6ul<<13),
  ADC12_CV_RepeatNum128 = (CSP_REGISTER_T)(0x7ul<<8)|(0x7ul<<13),
  ADC12_CV_RepeatNum256 = (CSP_REGISTER_T)(0x8ul<<8)|(0x8ul<<13),
  ADC12_CV_RepeatNum512 = (CSP_REGISTER_T)(0x9ul<<8)|(0x9ul<<13)
}ADC12_CV_RepeatNum_TypeDef;




typedef enum
{
 ADC12_VREFP_VDD_VREFN_VSS = 0,
 ADC12_VREFP_EXIT_VREFN_VSS = 1,
 ADC12_VREFP_FVR2048_VREFN_VSS = 2,
 ADC12_VREFP_FVR4096_VREFN_VSS = 3,

 ADC12_VREFP_INTVREF1000_VREFN_VSS = 5,
 ADC12_VREFP_VDD_VREFN_EXIT = 6,
 ADC12_VREFP_EXIT_VREFN_EXIT = 7,
 ADC12_VREFP_FVR2048_VREFN_EXIT = 8,
 ADC12_VREFP_FVR4096_VREFN_EXIT = 9,

 ADC12_VREFP_INTVREF1000_VREFN_EXIT = 11
}ADC12_VREFP_VREFN_Selected_TypeDef;

extern void ADC12_RESET_VALUE(void);
extern void ADC12_Control(ADC12_Control_TypeDef ADC12_Control_x );
extern void ADC12_ConfigInterrupt_CMD( ADC12_IMR_TypeDef ADC_IMR_X , FunctionalStatus NewState);
extern unsigned char ADC12_Read_IntEnStatus(ADC12_IMR_TypeDef EnStatus_bit);
extern void ADC12_CLK_CMD(ADC12_CLK_TypeDef ADC_CLK_CMD , FunctionalStatus NewState);
extern void ADC12_Software_Reset(void);
extern void ADC12_CMD(FunctionalStatus NewState);
extern void ADC12_ready_wait(void);
extern void ADC12_EOC_wait(void);
extern void ADC12_SEQEND_wait(U8_T val);
extern U16_T ADC12_DATA_OUPUT(U16_T Data_index );
extern void ADC12_Configure_Mode(ADC12_10bitor12bit_TypeDef ADC12_BIT_SELECTED , ADC12_ConverMode_TypeDef ADC12_ConverMode , U8_T ADC12_PRI, U8_T adc12_SHR , U8_T ADC12_DIV , U8_T NumConver );
extern void ADC12_Configure_VREF_Selecte(ADC12_VREFP_VREFN_Selected_TypeDef ADC12_VREFP_X_VREFN_X );
extern void ADC12_CompareFunction_set(U8_T ConverNum_CM0 , U8_T ConverNum_CM1 , U16_T CMP0_data , U16_T CMP1_data );
extern void ADC12_ConversionChannel_Config(ADC12_InputSet_TypeDef ADC12_ADCINX ,
      ADC12_CV_RepeatNum_TypeDef CV_RepeatTime, ADC12_Control_TypeDef AVG_Set, U8_T SEQx);
extern U8_T ADC12_Compare_statue(ADC12_NBRCMPx_TypeDef ADC12_NBRCMPx, ADC12_NBRCMPx_HorL_TypeDef ADC12_NBRCMPx_HorL);
extern void ADC_Int_Enable(void);
extern void ADC_Int_Disable(void);
extern void ADC12_CONFIG(void);
extern void adc12_SHR_SET(U8_T adc12_SHR);
# 20 "FWlib/apt32f102_adc.c" 2
# 28 "FWlib/apt32f102_adc.c"
void ADC12_RESET_VALUE(void)
{
  ADC0->ECR = (0x00000000ul);
  ADC0->DCR = (0x00000000ul);
  ADC0->PMSR = (0x00000000ul);
  ADC0->CR = (0x80000000ul);
  ADC0->MR = (0x00000000ul);
  ADC0->CSR = (0x00000000ul);
  ADC0->SR = (0x00000000ul);
  ADC0->IER = (0x00000000ul);
  ADC0->IDR = (0x00000000ul);
  ADC0->IMR = (0x00000000ul);
  ADC0->SEQ[0]= (0x00000080ul);
  ADC0->SEQ[1]= (0x00000080ul);
  ADC0->SEQ[2]= (0x00000080ul);
  ADC0->SEQ[3]= (0x00000080ul);
  ADC0->SEQ[4]= (0x00000080ul);
  ADC0->SEQ[5]= (0x00000080ul);
  ADC0->SEQ[6]= (0x00000080ul);
  ADC0->SEQ[7]= (0x00000080ul);
  ADC0->SEQ[8]= (0x00000080ul);
  ADC0->SEQ[9]= (0x00000080ul);
  ADC0->SEQ[10]= (0x00000080ul);
  ADC0->SEQ[11]= (0x00000080ul);
  ADC0->SEQ[12]= (0x00000080ul);
  ADC0->SEQ[13]= (0x00000080ul);
  ADC0->SEQ[14]= (0x00000080ul);
  ADC0->SEQ[15]= (0x00000080ul);
  ADC0->DR[0] = (0x00000000ul);
  ADC0->DR[1] = (0x00000000ul);
  ADC0->DR[2] = (0x00000000ul);
  ADC0->DR[3] = (0x00000000ul);
  ADC0->DR[4] = (0x00000000ul);
  ADC0->DR[5] = (0x00000000ul);
  ADC0->DR[6] = (0x00000000ul);
  ADC0->DR[7] = (0x00000000ul);
  ADC0->DR[8] = (0x00000000ul);
  ADC0->DR[9] = (0x00000000ul);
  ADC0->DR[10] = (0x00000000ul);
  ADC0->DR[11] = (0x00000000ul);
  ADC0->DR[12] = (0x00000000ul);
  ADC0->DR[13] = (0x00000000ul);
  ADC0->DR[14] = (0x00000000ul);
  ADC0->DR[15] = (0x00000000ul);
  ADC0->CMP0 = (0x00000000ul);
  ADC0->CMP1 = (0x00000000ul);
}







void ADC12_Control(ADC12_Control_TypeDef ADC12_Control_x )
{
 ADC0->CR |= ADC12_Control_x;
}
# 101 "FWlib/apt32f102_adc.c"
void ADC12_ConfigInterrupt_CMD( ADC12_IMR_TypeDef ADC_IMR_X , FunctionalStatus NewState)
{
 if (NewState != DISABLE)
 {
  ADC0->IER |= ADC_IMR_X;
 }
 else
 {
  ADC0->IDR |= ADC_IMR_X;
 }
}






unsigned char ADC12_Read_IntEnStatus(ADC12_IMR_TypeDef EnStatus_bit)
{
 unsigned char value = 0;
    unsigned int dat = 0;
    dat= ADC0->IMR&EnStatus_bit;
    if (dat == EnStatus_bit)
 {
     value = 1;
 }
    return value;
}







void ADC12_CLK_CMD(ADC12_CLK_TypeDef ADC_CLK_CMD , FunctionalStatus NewState)
{
 if (NewState != DISABLE)
 {
  ADC0->ECR |= ADC_CLK_CMD;
  while(!(ADC0->PMSR&ADC_CLK_CMD));
 }
 else
 {
  ADC0->DCR |= ADC_CLK_CMD;
  while(ADC0->PMSR&ADC_CLK_CMD);
 }
}





void ADC12_Software_Reset(void)
{
 ADC12_Control(ADC12_SWRST);
}






void ADC12_CMD(FunctionalStatus NewState)
{
 if (NewState != DISABLE)
 {
  ADC12_Control(ADC12_ADCEN);
  while(!(ADC0->SR &ADC12_ADCENS));
 }
 else
 {
  ADC12_Control(ADC12_ADCDIS);
  while(ADC0->SR&ADC12_ADCENS);
 }
}





void ADC12_ready_wait(void)
{
 while(!(ADC0->SR&ADC12_READY));
}





void ADC12_EOC_wait(void)
{
 while(!(ADC0->SR & ADC12_EOC));
}





void ADC12_SEQEND_wait(U8_T val)
{
 while(!(ADC0->SR & (0x01ul << (16+val))));
}





U16_T ADC12_DATA_OUPUT(U16_T Data_index )
{
 return(ADC0->DR[Data_index]);
}
# 228 "FWlib/apt32f102_adc.c"
void ADC12_Configure_Mode(ADC12_10bitor12bit_TypeDef ADC12_BIT_SELECTED , ADC12_ConverMode_TypeDef ADC12_ConverMode , U8_T ADC12_PRI, U8_T adc12_SHR , U8_T ADC12_DIV , U8_T NumConver )
{
 ADC0->MR=ADC12_DIV|((NumConver-1)<<10);
 if(ADC12_ConverMode==One_shot_mode)
 {
  ADC0->MR&=~CONTCV;
  while(ADC0->SR&ADC12_CTCVS);
 }
 else if(ADC12_ConverMode==Continuous_mode)
 {
  ADC0->MR|=CONTCV;
  while(!(ADC0->SR&ADC12_CTCVS));
 }
 ADC12_CMD(ENABLE);
 if(ADC12_BIT_SELECTED)
 {
  ADC0->CR|=ADC12_10BITor12BIT;
 }
 else
 {
  ADC0->CR&=~ADC12_10BITor12BIT;
 }

 ADC0->PRI=ADC12_PRI;
 ADC0->SHR=adc12_SHR;
}





void ADC12_Configure_VREF_Selecte(ADC12_VREFP_VREFN_Selected_TypeDef ADC12_VREFP_X_VREFN_X )
{
 if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_VDD_VREFN_VSS)
 {
  ADC0->CR=(ADC0->CR&0xfcfefc3f)|(0x00<<6);
 }
 else if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_EXIT_VREFN_VSS)
 {
  GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFF0FF) | 0x00000800;
  ADC0->CR=(ADC0->CR&0xfcfefc3f)|(0x01<<6);
 }
 else if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_FVR2048_VREFN_VSS)
 {
  GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFF0FF) | 0x00000800;
  ADC0->CR=(ADC0->CR&0xfcfefc3f)|(0x02<<6)|(0X01<<24)|(0X00<<25);
 }
 else if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_FVR4096_VREFN_VSS)
 {
  GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFF0FF) | 0x00000800;
  ADC0->CR=(ADC0->CR&0xfcfefc3f)|(0x03<<6)|(0X01<<24)|(0X01<<25);
 }
 else if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_INTVREF1000_VREFN_VSS)
 {
  ADC0->CR=(ADC0->CR&0xfcfefc3f)|(0x04<<6)|(0X00<<16)|(0X02<<17);
 }
 else if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_VDD_VREFN_EXIT)
 {
  GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0x00008000;
  ADC0->CR=(ADC0->CR&0xfcfefc3f)|(0x08<<6);
 }
 else if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_EXIT_VREFN_EXIT)
 {
  GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0x00008000;
  GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFF0FF) | 0x00000800;
  ADC0->CR=(ADC0->CR&0xfcfefc3f)|(0x09<<6);
 }
 else if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_FVR2048_VREFN_EXIT)
 {
  GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0x00008000;
  GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFF0FF) | 0x00000800;
  ADC0->CR=(ADC0->CR&0xfcfefc3f)|(0x0A<<6)|(0X01<<24)|(0X00<<25);
 }
 else if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_FVR4096_VREFN_EXIT)
 {
  GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0x00008000;
  GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFF0FF) | 0x00000800;
  ADC0->CR=(ADC0->CR&0xfcfefc3f)|(0x0B<<6)|(0X01<<24)|(0X01<<25);
 }
 else if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_INTVREF1000_VREFN_EXIT)
 {
  GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0x00008000;
  ADC0->CR=(ADC0->CR&0xfcfefc3f)|(0x0C<<6)|(0X00<<16)|(0X02<<17);
 }
}
# 328 "FWlib/apt32f102_adc.c"
void ADC12_CompareFunction_set(U8_T ConverNum_CM0 , U8_T ConverNum_CM1 , U16_T CMP0_data , U16_T CMP1_data )
{
 ADC0->MR|=((ConverNum_CM0-0)<<16)|((ConverNum_CM1-0)<<22);
 ADC0->CMP0=CMP0_data;
 ADC0->CMP1=CMP1_data;
}







void ADC12_ConversionChannel_Config(ADC12_InputSet_TypeDef ADC12_ADCINX ,
      ADC12_CV_RepeatNum_TypeDef CV_RepeatTime, ADC12_Control_TypeDef AVG_Set, U8_T SEQx)
{
 switch(ADC12_ADCINX)
 {
  case 0:
   GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000;
   GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0x00000000;
   GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFF0F) | 0x00000010;
   break;
  case 1:
   GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFF0) | 0x00000001;
   GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0x00000000;
   GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000;
   break;
  case 2:
   GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFF0F) | 0x00000010;
   GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0x00000000;
   GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000;
   break;
  case 3:
   GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0x00001000;
   GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0x00000000;
   GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000;
   break;
  case 4:
   GPIOA0->CONLR = (GPIOA0->CONLR&0XFF0FFFFF) | 0x00100000;
   GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0x00000000;
   GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000;
   break;
  case 5:
   GPIOA0->CONLR = (GPIOA0->CONLR&0XF0FFFFFF) | 0x01000000;
   GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0x00000000;
   GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000;
   break;
  case 6:
   GPIOA0->CONLR = (GPIOA0->CONLR&0X0FFFFFFF) | 0x10000000;
   GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0x00000000;
   GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000;
   break;
  case 7:
   GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000;
   GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0x00000000;
   GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFF0FF) | 0x00000100;
   break;
  case 8:
   GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000;
   GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0x00000000;
   GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFF0FFF) | 0x00001000;
   break;
  case 9:
   GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000;
   GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFF0) | 0x00000001;
   GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000;
   break;
  case 10:
   GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000;
   GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFF0F) | 0x00000010;
   GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000;
   break;
  case 11:
   GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000;
   GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFF0FF) | 0x00000100;
   GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000;
   break;
  case 12:
   GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000;
   GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFF0FFF) | 0x00001000;
   GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000;
   break;
  case 13:
   GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000;
   GPIOA0->CONHR = (GPIOA0->CONHR&0XFFF0FFFF) | 0x00010000;
   GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000;
   break;
  case 14:
   GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000;
   GPIOA0->CONHR = (GPIOA0->CONHR&0XFF0FFFFF) | 0x00100000;
   GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000;
   break;
  case 15:
   GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000;
   GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0x00000000;
   GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFF0) | 0x00000001;
   break;
# 436 "FWlib/apt32f102_adc.c"
  case 0x1Cul: break;
  case 0x1Dul: break;
  case 0x1Eul: break;
 }
 ADC0->SEQ[SEQx] = ADC0->SEQ[SEQx] & 0;
 ADC0->SEQ[SEQx] = ADC0->SEQ[SEQx] | ADC12_ADCINX | CV_RepeatTime | AVG_Set;
}
# 451 "FWlib/apt32f102_adc.c"
U8_T ADC12_Compare_statue(ADC12_NBRCMPx_TypeDef ADC12_NBRCMPx, ADC12_NBRCMPx_HorL_TypeDef ADC12_NBRCMPx_HorL)
{
 if(ADC12_NBRCMPx==NBRCMP0_TypeDef)
 {
  if(ADC12_NBRCMPx_HorL==NBRCMPX_L_TypeDef)
  {
   return((ADC0->SR)&ADC12_CMP0L);
  }
  else
  {
   return((ADC0->SR)&ADC12_CMP0H);
  }

 }
 else
 {
  if(ADC12_NBRCMPx_HorL==NBRCMPX_L_TypeDef)
  {
   return((ADC0->SR)&ADC12_CMP1L);
  }
  else
  {
   return((ADC0->SR)&ADC12_CMP1H);
  }
 }
}





void ADC_Int_Enable(void)
{
    ADC0->CSR=0xFFFFFFFF;
 *(volatile UINT32 *) (0xE000E000 +0x100 ) = (0x01ul<<3);
}





void ADC_Int_Disable(void)
{
    *(volatile UINT32 *) (0xE000E000 +0x180 ) = (0x01ul<<3);
}
